Fewer than 5 people recommend it so far, so there's no written verdict. Here is what commenters said.

3recommend
0warn against
Mar 21, 2026first mention
Jul 24, 2026latest mention
Nov 25 – Oct 26
Used forverilog simulationdigital chip designsimulating rtl designsrisc-v project simulation

Why people recommend it

“I hope people give the Verilator simulations a try”

Show 1 more

“I used Verilator for a risc-v project in university and it was excellent, substantially faster than Yosys”

Caveats and dissent

No one in these comments warned against it.

Often compared with

Who recommends it in their own words

All comments 4

“This used the librelane classic flow, so it's a lot of verilator, yosys, openroad, opensta, magic and klayout.”

“I hope people give the Verilator simulations a try”

“I used Verilator for a risc-v project in university and it was excellent, substantially faster than Yosys”

Threads where it came up

Data: verilator.json. Quotes are verbatim; the verdict and theme labels are written by a model from these comments, and every clause links to its sources.

Keyboard shortcuts
j / kNext / previous item
o or EnterOpen selected item
/Search
g hHome
g tTop
g rRising
g cCategories
tToggle dark mode
?This help