{"slug": "verilator", "name": "Verilator", "category": "other", "category_name": "Other software", "description": "", "recommenders": 3, "commenters": 4, "warners": 0, "score": 2.94, "rising": -0.98, "first": "2026-03-21", "latest": "2026-07-24", "why": "I used Verilator for a risc-v project in university and it was excellent, substantially faster than Yosys", "why_is_quote": true, "has_verdict": false, "sentiment": {"recommend": 3, "neutral": 1, "compare": 0, "warn": 0}, "spark": [0, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0, 0], "listed": true, "loved": [], "caveat": "", "short_quote": "I used Verilator for a risc-v project in university and it was excellent, substantially faster than Yosys", "kind": "", "icon": true, "domain": null, "github_repo": null, "official_url": "https://www.veripool.org/verilator/", "pricing": "", "aliases": ["Verilator"], "verdict": null, "praise": [{"label": "", "summary": "", "quotes": [{"id": 778656785, "item_id": 48666049, "url": "https://news.ycombinator.com/item?id=48666049", "by": "y1n0", "date": "2026-06-24", "version": null, "stance": "recommend", "quote": "for tools, check out verilator", "excerpt": "For digital chip design, research Verilog and/or SystemVerilog, and for tools, check out verilator and the OSS cad suite: https://github.com/YosysHQ/oss-cad-suite-build", "context": "", "use_case": "digital chip design", "switched_from": "", "story": "OpenAI unveils its first custom chip, built by Broadcom"}, {"id": 759894944, "item_id": 47493434, "url": "https://news.ycombinator.com/item?id=47493434", "by": "bunnie", "date": "2026-03-23", "version": null, "stance": "recommend", "quote": "I hope people give the Verilator simulations a try", "excerpt": "The idea of the wait-to-quantum register is that it gets you out of cycle-counting hell at the expense of sacrificing a few cycles as rounding errors. But yes, for maximum performance you would be back to cycle counting. That being said - one nice thing about the BIO being open source is you can run the verilog design in Verilator. The simulation shows exactly how many cycles are being used, and for what. So for very", "context": "", "use_case": "simulating RTL designs", "switched_from": "", "story": "BIO: The Bao I/O Coprocessor"}, {"id": 759563568, "item_id": 47472723, "url": "https://news.ycombinator.com/item?id=47472723", "by": "Bolwin", "date": "2026-03-21", "version": null, "stance": "recommend", "quote": "I used Verilator for a risc-v project in university and it was excellent, substantially faster than Yosys", "excerpt": "I don't know a ton about this field (though I'm curious, if anyone had recommended material) but I used Verilator for a risc-v project in university and it was excellent, substantially faster than Yosys", "context": "university student project", "use_case": "RISC-V project simulation", "switched_from": "", "story": "Verilator open-source SystemVerilog simulator"}]}], "caveats": [], "who": [{"by": "Bolwin", "context": "university student project", "url": "https://news.ycombinator.com/item?id=47472723", "date": "2026-03-21"}], "tags": [], "use_cases": ["verilog simulation", "digital chip design", "simulating rtl designs", "risc-v project simulation"], "compared": [{"slug": "yosys", "name": "Yosys", "co": 2, "switched_from": 0, "switched_to": 0}], "makers": [], "threads": [{"url": "https://news.ycombinator.com/item?id=48985182", "title": "Designing an Ethernet Switch ASIC", "mentions": 1}, {"url": "https://news.ycombinator.com/item?id=48663324", "title": "OpenAI unveils its first custom chip, built by Broadcom", "mentions": 1}, {"url": "https://news.ycombinator.com/item?id=47459363", "title": "BIO: The Bao I/O Coprocessor", "mentions": 1}, {"url": "https://news.ycombinator.com/item?id=47460686", "title": "Verilator open-source SystemVerilog simulator", "mentions": 1}], "sentiment_by_month": {"2025-11": {}, "2025-12": {}, "2026-01": {}, "2026-02": {}, "2026-03": {"recommend": 2}, "2026-04": {}, "2026-05": {}, "2026-06": {"recommend": 1}, "2026-07": {"neutral": 1}, "2026-08": {}, "2026-09": {}, "2026-10": {}}, "versions": [], "version_unnamed": 0, "quotes": [{"id": 784677745, "item_id": 49042359, "url": "https://news.ycombinator.com/item?id=49042359", "by": "random__duck", "date": "2026-07-24", "version": null, "stance": "neutral", "quote": "This used the librelane classic flow, so it's a lot of verilator, yosys, openroad, opensta, magic and klayout.", "excerpt": "True, I went over the EDA stack a bit in a previous article here: https://talesonthewire.com/projects/blake2s_hashing_accelerator_a_solo_tapeout_journey/#open-source-silicon This used the librelane classic flow, so it's a lot of verilator, yosys, openroad, opensta, magic and klayout. :)", "context": "", "use_case": "Verilog simulation", "switched_from": "", "story": "Designing an Ethernet Switch ASIC"}, {"id": 778656785, "item_id": 48666049, "url": "https://news.ycombinator.com/item?id=48666049", "by": "y1n0", "date": "2026-06-24", "version": null, "stance": "recommend", "quote": "for tools, check out verilator", "excerpt": "For digital chip design, research Verilog and/or SystemVerilog, and for tools, check out verilator and the OSS cad suite: https://github.com/YosysHQ/oss-cad-suite-build", "context": "", "use_case": "digital chip design", "switched_from": "", "story": "OpenAI unveils its first custom chip, built by Broadcom"}, {"id": 759894944, "item_id": 47493434, "url": "https://news.ycombinator.com/item?id=47493434", "by": "bunnie", "date": "2026-03-23", "version": null, "stance": "recommend", "quote": "I hope people give the Verilator simulations a try", "excerpt": "The idea of the wait-to-quantum register is that it gets you out of cycle-counting hell at the expense of sacrificing a few cycles as rounding errors. But yes, for maximum performance you would be back to cycle counting. That being said - one nice thing about the BIO being open source is you can run the verilog design in Verilator. The simulation shows exactly how many cycles are being used, and for what. So for very", "context": "", "use_case": "simulating RTL designs", "switched_from": "", "story": "BIO: The Bao I/O Coprocessor"}, {"id": 759563568, "item_id": 47472723, "url": "https://news.ycombinator.com/item?id=47472723", "by": "Bolwin", "date": "2026-03-21", "version": null, "stance": "recommend", "quote": "I used Verilator for a risc-v project in university and it was excellent, substantially faster than Yosys", "excerpt": "I don't know a ton about this field (though I'm curious, if anyone had recommended material) but I used Verilator for a risc-v project in university and it was excellent, substantially faster than Yosys", "context": "university student project", "use_case": "RISC-V project simulation", "switched_from": "", "story": "Verilator open-source SystemVerilog simulator"}]}